module fulladder16(A,B,CI,SUM,CO);
	input [15:0] A;
	input [15:0] B;
	input CI;
	output [15:0] SUM;
	output CO;
	wire c1,c2,c3;

	adder4 instance1(A[3:0],B[3:0],CI,SUM[3:0],c1);
	adder4 instance2(A[7:4],B[7:4],c1,SUM[7:4],c2);
	adder4 instance3(A[11:8],B[11:8],c2,SUM[11:8],c3);
	adder4 instance4(A[15:12],B[15:12],c3,SUM[15:12],CO);

endmodule
